Many prior art printed circuit board connectors are constructed so that the pins on a connector lie at the edge of the board. The pc board typically contains the logic chips and is often called a daughter board. The daughter board plugs into a board called a mother board or the backplane which receives a plurality of daughter boards. The mother board has sockets aligned to receive the edge connectors on the daughter board. The mother board is typically positioned in a plane perpendicular to the plane of the daughter boards and provides the power and signal connections between the daughter boards.
As computers became more sophisticated, it became desirous to increase the number of pins on each edge connector between each daughter board and mother board. To minimally affect the spacing between boards connected to a backplane, the pins were reduced in size to increase packing density on each edge connector. However, as the pin size decreases, the electrical impedance of the pin increases, therefore, due to minimum current handling requirements, there is a lower limit to the pin size. Consequently, it became necessary to increase the number of pins on each edge connector by a method other than decreasing the pin size.
One prior art technique to increase the number of edge pins is to align a second set of pins parallel to the first set of pins but separated by a small distance; i.e., the added row of pins are raised off the face of the daughter board, but parallel to the board. The mother board has a parallel set of receptors aligned to receive the second set of pins. As the number of pins required increases, additional rows may be added. However, the number of rows of pins that may be added is limited by the amount of space between daughter boards. The plane of each daughter board is usually parallel to the plane of every other daughter board. Thus, as the number of rows of edge pins is increased, the space between daughter boards must be increased to accommodate the additional connector spacing requirements. However, the spacing between daughter boards must be kept to a minimum to minimize the electrical path lengths between logic components and thereby minimize signal propagation delay. Therefore, it is not practical to continue increasing the size of the mother board and increasing the spacing between daughter boards.
Many prior art edge pin connectors typically require a small, but finite amount of force to insert each pin. In super-computers such as the type manufactured by the assignee of the present invention, the daughter boards require many pin connections, and so it is important to employ a connector which allows the board to be inserted with zero insertion force since, if a pin has a non-zero insertion force the total insertion force for a board having thousands of pins becomes prohibitive.
High-speed computers require connectors that have minimal impedance interfaces (impedance changes through the connector) because an impedance interface may cause a partial reflection of a transmitted signal along an electrical path. This causes a cancelling voltage to be seen at the transmitter and a reduced voltage seen at the receiver. If the reflection is severe the receiver may not receive the proper signal and a transient fault would occur. In super-computers operating at a high frequency it is extremely important to minimize or avoid impedance interfaces because the magnitude of the reflected wave is frequency dependent. Since impedance itself is frequency dependent, the magnitude of a reflected wave at an impedance interface changes as frequency increases. An impedance interface that is acceptable at a low frequency may cause an error in data transmission at a higher frequency. As a result, data dependent errors may be caused by impedance interfaces depending upon the effective frequency of data transmitted through the interface. If the data consists of a one followed by several zeroes followed by a one, the effective frequency for impedance and reflection purposes will be lower than the peak operating frequency. If the data consists of alternating ones and zeros, the effective frequency for impedance and reflection purposes will be the peak operating frequency of the computer. Thus, an impedance change or mismatch at a connector interface may cause an error in data transmission for only some data.
Thus, there is a need in the prior art for high density edge connections between pc boars and backplanes which allows a high packing density of pins and yet does not increase the overall spacing between the pc boards on the backplane. There is also a need in the prior art for a high density edge connection scheme which allows boards to be placed and interconnected to the backplane with zero insertion force. There is also a need in the prior art to provide a very short electrical path between the PC boards and the backplane. There is also a need in the prior art for a high density pin edge connection scheme that imposes a minimum of impedance mismatching at the connector interface so that the electrical path between a signal transmitter and a signal receiver passing through the backplane is not subject to signal reflections due to impedance mismatches.